x64 / ntdllntoskrnl

_FADT

← 10.0.28000.3231 8 builds latest →
struct _FADT {
unsigned long facs;/* 0x24 4 */
unsigned long dsdt;/* 0x28 4 */
unsigned char int_model;/* 0x2c 1 */
unsigned char pm_profile;/* 0x2d 1 */
unsigned short sci_int_vector;/* 0x2e 2 */
unsigned long smi_cmd_io_port;/* 0x30 4 */
unsigned char acpi_on_value;/* 0x34 1 */
unsigned char acpi_off_value;/* 0x35 1 */
unsigned char s4bios_req;/* 0x36 1 */
unsigned char pstate_control;/* 0x37 1 */
unsigned long pm1a_evt_blk_io_port;/* 0x38 4 */
unsigned long pm1b_evt_blk_io_port;/* 0x3c 4 */
/* ── cacheline 1 boundary (64 bytes) ── */
unsigned long pm1a_ctrl_blk_io_port;/* 0x40 4 */
unsigned long pm1b_ctrl_blk_io_port;/* 0x44 4 */
unsigned long pm2_ctrl_blk_io_port;/* 0x48 4 */
unsigned long pm_tmr_blk_io_port;/* 0x4c 4 */
unsigned long gp0_blk_io_port;/* 0x50 4 */
unsigned long gp1_blk_io_port;/* 0x54 4 */
unsigned char pm1_evt_len;/* 0x58 1 */
unsigned char pm1_ctrl_len;/* 0x59 1 */
unsigned char pm2_ctrl_len;/* 0x5a 1 */
unsigned char pm_tmr_len;/* 0x5b 1 */
unsigned char gp0_blk_len;/* 0x5c 1 */
unsigned char gp1_blk_len;/* 0x5d 1 */
unsigned char gp1_base;/* 0x5e 1 */
unsigned char cstate_control;/* 0x5f 1 */
unsigned short lvl2_latency;/* 0x60 2 */
unsigned short lvl3_latency;/* 0x62 2 */
unsigned short flush_size;/* 0x64 2 */
unsigned short flush_stride;/* 0x66 2 */
unsigned char duty_offset;/* 0x68 1 */
unsigned char duty_width;/* 0x69 1 */
unsigned char day_alarm_index;/* 0x6a 1 */
unsigned char month_alarm_index;/* 0x6b 1 */
unsigned char century_alarm_index;/* 0x6c 1 */
unsigned short boot_arch;/* 0x6d 2 */
unsigned char reserved3[1];/* 0x6f 1 */
unsigned long flags;/* 0x70 4 */
/* ── cacheline 2 boundary (128 bytes) ── */
unsigned char reset_val;/* 0x80 1 */
unsigned short arm_boot_arch;/* 0x81 2 */
unsigned char minor_version_number;/* 0x83 1 */
/* ── cacheline 3 boundary (192 bytes) ── */
/* ── cacheline 4 boundary (256 bytes) ── */
unsigned __int64 hypervisor_vendor_identity;/* 0x10c 8 */
};
size 276 (0x114)56 members0 holespadding 05 cachelines