_HALP_DMA_CONTROLLER

Metadatacopy
struct _HALP_DMA_CONTROLLER {
    struct _LIST_ENTRY Controllers;/* 0x0  16 */
    struct _LIST_ENTRY AdapterList;/* 0x10  16 */
    unsigned long ControllerId;/* 0x20  4 */
    unsigned long MinimumRequestLine;/* 0x24  4 */
    unsigned long MaximumRequestLine;/* 0x28  4 */
    unsigned long ChannelCount;/* 0x2c  4 */
    unsigned long ScatterGatherLimit;/* 0x30  4 */
    /* 4 bytes padding */
    struct _HALP_DMA_CHANNEL* Channels;/* 0x38  8 */
    /* ── cacheline 1 boundary (64 bytes) ── */
    void* ExtensionData;/* 0x40  8 */
    unsigned char CacheCoherent;/* 0x48  1 */
    /* 3 bytes padding */
    unsigned long DmaAddressWidth;/* 0x4c  4 */
    struct _DMA_FUNCTION_TABLE Operations;/* 0x50  80 */
    /* ── cacheline 2 boundary (128 bytes) ── */
    unsigned long SupportedPortWidths;/* 0xa0  4 */
    unsigned long MinimumTransferUnit;/* 0xa4  4 */
    unsigned __int64 Lock;/* 0xa8  8 */
    unsigned char Irql;/* 0xb0  1 */
    unsigned char GeneratesInterrupt;/* 0xb1  1 */
    /* 2 bytes padding */
    long Gsi;/* 0xb4  4 */
    enum _KINTERRUPT_POLARITY InterruptPolarity;/* 0xb8  4 */
    enum _KINTERRUPT_MODE InterruptMode;/* 0xbc  4 */
    /* ── cacheline 3 boundary (192 bytes) ── */
    struct _UNICODE_STRING ResourceId;/* 0xc0  16 */
    struct POHANDLE__* PowerHandle;/* 0xd0  8 */
    unsigned char PowerActive;/* 0xd8  1 */
};