x64x86arm64 / ntdllntoskrnl

HAL_PRIVATE_DISPATCH

← 10.0.18362.1016 4 builds latest →
struct HAL_PRIVATE_DISPATCH {
unsigned long Version;/* 0x0 4 */
struct _BUS_HANDLER* (*HalHandlerForBus)(enum _INTERFACE_TYPE, unsigned long);/* 0x4 4 */
struct _BUS_HANDLER* (*HalHandlerForConfigSpace)(enum _BUS_DATA_TYPE, unsigned long);/* 0x8 4 */
void (*HalLocateHiberRanges)(void*);/* 0xc 4 */
long (*HalRegisterBusHandler)(enum _INTERFACE_TYPE, enum _BUS_DATA_TYPE, unsigned long, enum _INTERFACE_TYPE, unsigned long, unsigned long, long (*)(struct _BUS_HANDLER*), struct _BUS_HANDLER**);/* 0x10 4 */
void (*HalSetWakeEnable)(unsigned char);/* 0x14 4 */
long (*HalSetWakeAlarm)(unsigned __int64, unsigned __int64);/* 0x18 4 */
unsigned char (*HalPciTranslateBusAddress)(enum _INTERFACE_TYPE, unsigned long, union _LARGE_INTEGER, unsigned long*, union _LARGE_INTEGER*);/* 0x1c 4 */
long (*HalPciAssignSlotResources)(struct _UNICODE_STRING*, struct _UNICODE_STRING*, struct _DRIVER_OBJECT*, struct _DEVICE_OBJECT*, enum _INTERFACE_TYPE, unsigned long, unsigned long, struct _CM_RESOURCE_LIST**);/* 0x20 4 */
void (*HalHaltSystem)(void);/* 0x24 4 */
unsigned char (*HalFindBusAddressTranslation)(union _LARGE_INTEGER, unsigned long*, union _LARGE_INTEGER*, unsigned long*, unsigned char);/* 0x28 4 */
unsigned char (*HalResetDisplay)(void);/* 0x2c 4 */
long (*HalAllocateMapRegisters)(struct _ADAPTER_OBJECT*, unsigned long, unsigned long, struct _MAP_REGISTER_ENTRY*);/* 0x30 4 */
long (*KdSetupPciDeviceForDebugging)(void*, struct _DEBUG_DEVICE_DESCRIPTOR*);/* 0x34 4 */
long (*KdReleasePciDeviceForDebugging)(struct _DEBUG_DEVICE_DESCRIPTOR*);/* 0x38 4 */
void* (*KdGetAcpiTablePhase0)(struct _LOADER_PARAMETER_BLOCK*, unsigned long);/* 0x3c 4 */
/* ── cacheline 1 boundary (64 bytes) ── */
void (*KdCheckPowerButton)(void);/* 0x40 4 */
unsigned char (*HalVectorToIDTEntry)(unsigned long);/* 0x44 4 */
void* (*KdMapPhysicalMemory64)(union _LARGE_INTEGER, unsigned long, unsigned char);/* 0x48 4 */
void (*KdUnmapVirtualAddress)(void*, unsigned long, unsigned char);/* 0x4c 4 */
unsigned long (*KdGetPciDataByOffset)(unsigned long, unsigned long, void*, unsigned long, unsigned long);/* 0x50 4 */
unsigned long (*KdSetPciDataByOffset)(unsigned long, unsigned long, void*, unsigned long, unsigned long);/* 0x54 4 */
unsigned long (*HalGetInterruptVectorOverride)(enum _INTERFACE_TYPE, unsigned long, unsigned long, unsigned long, unsigned char*, unsigned long*);/* 0x58 4 */
long (*HalGetVectorInputOverride)(unsigned long, struct _GROUP_AFFINITY*, unsigned long*, enum _KINTERRUPT_POLARITY*, struct _INTERRUPT_REMAPPING_INFO*);/* 0x5c 4 */
long (*HalLoadMicrocode)(void*);/* 0x60 4 */
long (*HalUnloadMicrocode)(void);/* 0x64 4 */
long (*HalPostMicrocodeUpdate)(void);/* 0x68 4 */
long (*HalAllocateMessageTargetOverride)(struct _DEVICE_OBJECT*, struct _GROUP_AFFINITY*, unsigned long, enum _KINTERRUPT_MODE, unsigned char, unsigned long*, unsigned char*, unsigned long*);/* 0x6c 4 */
void (*HalFreeMessageTargetOverride)(struct _DEVICE_OBJECT*, unsigned long, struct _GROUP_AFFINITY*);/* 0x70 4 */
long (*HalDpReplaceBegin)(struct _HAL_DP_REPLACE_PARAMETERS*, void**);/* 0x74 4 */
void (*HalDpReplaceTarget)(void*);/* 0x78 4 */
long (*HalDpReplaceControl)(unsigned long, void*);/* 0x7c 4 */
/* ── cacheline 2 boundary (128 bytes) ── */
void (*HalDpReplaceEnd)(void*);/* 0x80 4 */
void (*HalPrepareForBugcheck)(unsigned long);/* 0x84 4 */
unsigned char (*HalQueryWakeTime)(unsigned __int64*, unsigned __int64*);/* 0x88 4 */
void (*HalReportIdleStateUsage)(unsigned char, struct _KAFFINITY_EX*);/* 0x8c 4 */
void (*HalTscSynchronization)(unsigned char, unsigned long*);/* 0x90 4 */
long (*HalWheaInitProcessorGenericSection)(struct _WHEA_ERROR_RECORD_SECTION_DESCRIPTOR*, struct _WHEA_PROCESSOR_GENERIC_ERROR_SECTION*);/* 0x94 4 */
void (*HalStopLegacyUsbInterrupts)(enum _SYSTEM_POWER_STATE);/* 0x98 4 */
long (*HalReadWheaPhysicalMemory)(union _LARGE_INTEGER, unsigned long, void*);/* 0x9c 4 */
long (*HalWriteWheaPhysicalMemory)(union _LARGE_INTEGER, unsigned long, void*);/* 0xa0 4 */
long (*HalDpMaskLevelTriggeredInterrupts)(void);/* 0xa4 4 */
long (*HalDpUnmaskLevelTriggeredInterrupts)(void);/* 0xa8 4 */
long (*HalDpGetInterruptReplayState)(void*, void**);/* 0xac 4 */
long (*HalDpReplayInterrupts)(void*);/* 0xb0 4 */
unsigned char (*HalQueryIoPortAccessSupported)(void);/* 0xb4 4 */
long (*KdSetupIntegratedDeviceForDebugging)(void*, struct _DEBUG_DEVICE_DESCRIPTOR*);/* 0xb8 4 */
long (*KdReleaseIntegratedDeviceForDebugging)(struct _DEBUG_DEVICE_DESCRIPTOR*);/* 0xbc 4 */
/* ── cacheline 3 boundary (192 bytes) ── */
void (*HalGetEnlightenmentInformation)(struct _HAL_INTEL_ENLIGHTENMENT_INFORMATION*);/* 0xc0 4 */
void* (*HalAllocateEarlyPages)(struct _LOADER_PARAMETER_BLOCK*, unsigned long, unsigned __int64*, unsigned long);/* 0xc4 4 */
void* (*HalMapEarlyPages)(unsigned __int64, unsigned long, unsigned long);/* 0xc8 4 */
void* Dummy1;/* 0xcc 4 */
void* Dummy2;/* 0xd0 4 */
void (*HalNotifyProcessorFreeze)(unsigned char, unsigned char);/* 0xd4 4 */
long (*HalPrepareProcessorForIdle)(unsigned long);/* 0xd8 4 */
void (*HalRegisterLogRoutine)(struct _HAL_LOG_REGISTER_CONTEXT*);/* 0xdc 4 */
void (*HalResumeProcessorFromIdle)(void);/* 0xe0 4 */
void* Dummy;/* 0xe4 4 */
unsigned long (*HalVectorToIDTEntryEx)(unsigned long);/* 0xe8 4 */
long (*HalSecondaryInterruptQueryPrimaryInformation)(struct _INTERRUPT_VECTOR_DATA*, unsigned long*);/* 0xec 4 */
long (*HalMaskInterrupt)(unsigned long, unsigned long);/* 0xf0 4 */
long (*HalUnmaskInterrupt)(unsigned long, unsigned long);/* 0xf4 4 */
unsigned char (*HalIsInterruptTypeSecondary)(unsigned long, unsigned long);/* 0xf8 4 */
long (*HalAllocateGsivForSecondaryInterrupt)(char*, unsigned short, unsigned long*);/* 0xfc 4 */
/* ── cacheline 4 boundary (256 bytes) ── */
long (*HalAddInterruptRemapping)(unsigned long, unsigned long, struct _PCI_BUSMASTER_DESCRIPTOR*, unsigned char, struct _INTERRUPT_VECTOR_DATA*, unsigned long);/* 0x100 4 */
void (*HalRemoveInterruptRemapping)(unsigned long, unsigned long, struct _PCI_BUSMASTER_DESCRIPTOR*, unsigned char, struct _INTERRUPT_VECTOR_DATA*, unsigned long);/* 0x104 4 */
void (*HalSaveAndDisableHvEnlightenment)(void);/* 0x108 4 */
void (*HalRestoreHvEnlightenment)(void);/* 0x10c 4 */
void (*HalFlushIoBuffersExternalCache)(struct _MDL*, unsigned char);/* 0x110 4 */
void (*HalFlushExternalCache)(unsigned char);/* 0x114 4 */
long (*HalPciEarlyRestore)(enum _SYSTEM_POWER_STATE);/* 0x118 4 */
long (*HalGetProcessorId)(unsigned long, unsigned long*, unsigned long*);/* 0x11c 4 */
long (*HalAllocatePmcCounterSet)(unsigned long, enum _KPROFILE_SOURCE*, unsigned long, struct _HAL_PMC_COUNTERS**);/* 0x120 4 */
void (*HalCollectPmcCounters)(struct _HAL_PMC_COUNTERS*, unsigned __int64*);/* 0x124 4 */
void (*HalFreePmcCounterSet)(struct _HAL_PMC_COUNTERS*);/* 0x128 4 */
long (*HalProcessorHalt)(unsigned long, void*, long (*)(void*));/* 0x12c 4 */
unsigned __int64 (*HalTimerQueryCycleCounter)(unsigned __int64*);/* 0x130 4 */
void* Dummy3;/* 0x134 4 */
void (*HalPciMarkHiberPhase)(void);/* 0x138 4 */
long (*HalQueryProcessorRestartEntryPoint)(union _LARGE_INTEGER*);/* 0x13c 4 */
/* ── cacheline 5 boundary (320 bytes) ── */
long (*HalRequestInterrupt)(unsigned long);/* 0x140 4 */
long (*HalEnumerateUnmaskedInterrupts)(unsigned char (*)(void*, struct _HAL_UNMASKED_INTERRUPT_INFORMATION*), void*, struct _HAL_UNMASKED_INTERRUPT_INFORMATION*);/* 0x144 4 */
void (*HalFlushAndInvalidatePageExternalCache)(union _LARGE_INTEGER);/* 0x148 4 */
long (*KdEnumerateDebuggingDevices)(void*, struct _DEBUG_DEVICE_DESCRIPTOR*, enum KD_CALLBACK_ACTION (*)(struct _DEBUG_DEVICE_DESCRIPTOR*));/* 0x14c 4 */
void (*HalFlushIoRectangleExternalCache)(struct _MDL*, unsigned long, unsigned long, unsigned long, unsigned long, unsigned char);/* 0x150 4 */
void (*HalPowerEarlyRestore)(unsigned long);/* 0x154 4 */
long (*HalQueryCapsuleCapabilities)(void*, unsigned long, unsigned __int64*, unsigned long*);/* 0x158 4 */
long (*HalUpdateCapsule)(void*, unsigned long, union _LARGE_INTEGER);/* 0x15c 4 */
unsigned char (*HalPciMultiStageResumeCapable)(void);/* 0x160 4 */
void (*HalDmaFreeCrashDumpRegisters)(unsigned long);/* 0x164 4 */
unsigned char (*HalAcpiAoacCapable)(void);/* 0x168 4 */
long (*HalInterruptSetDestination)(struct _INTERRUPT_VECTOR_DATA*, struct _GROUP_AFFINITY*, unsigned long*);/* 0x16c 4 */
void (*HalGetClockConfiguration)(struct _HAL_CLOCK_TIMER_CONFIGURATION*);/* 0x170 4 */
void (*HalClockTimerActivate)(unsigned char);/* 0x174 4 */
void (*HalClockTimerInitialize)(void);/* 0x178 4 */
void (*HalClockTimerStop)(void);/* 0x17c 4 */
/* ── cacheline 6 boundary (384 bytes) ── */
long (*HalClockTimerArm)(enum _HAL_CLOCK_TIMER_MODE, unsigned __int64, unsigned __int64*);/* 0x180 4 */
unsigned char (*HalTimerOnlyClockInterruptPending)(void);/* 0x184 4 */
void* (*HalAcpiGetMultiNode)(void);/* 0x188 4 */
void (* (*HalPowerSetRebootHandler)(void (*)(unsigned long, volatile long*));/* 0x18c 4 */
void (*HalIommuRegisterDispatchTable)(struct _HAL_IOMMU_DISPATCH*);/* 0x190 4 */
void (*HalTimerWatchdogStart)(void);/* 0x194 4 */
void (*HalTimerWatchdogResetCountdown)(void);/* 0x198 4 */
void (*HalTimerWatchdogStop)(void);/* 0x19c 4 */
unsigned char (*HalTimerWatchdogGeneratedLastReset)(void);/* 0x1a0 4 */
long (*HalTimerWatchdogTriggerSystemReset)(unsigned char);/* 0x1a4 4 */
long (*HalInterruptVectorDataToGsiv)(struct _INTERRUPT_VECTOR_DATA*, unsigned long*);/* 0x1a8 4 */
long (*HalInterruptGetHighestPriorityInterrupt)(unsigned long*, unsigned char*);/* 0x1ac 4 */
long (*HalProcessorOn)(unsigned long);/* 0x1b0 4 */
long (*HalProcessorOff)(void);/* 0x1b4 4 */
long (*HalProcessorFreeze)(void);/* 0x1b8 4 */
long (*HalDmaLinkDeviceObjectByToken)(unsigned long, struct _DEVICE_OBJECT*);/* 0x1bc 4 */
/* ── cacheline 7 boundary (448 bytes) ── */
long (*HalDmaCheckAdapterToken)(unsigned long);/* 0x1c0 4 */
void* Dummy4;/* 0x1c4 4 */
long (*HalTimerConvertPerformanceCounterToAuxiliaryCounter)(unsigned __int64, unsigned __int64*, unsigned __int64*);/* 0x1c8 4 */
long (*HalTimerConvertAuxiliaryCounterToPerformanceCounter)(unsigned __int64, unsigned __int64*, unsigned __int64*);/* 0x1cc 4 */
long (*HalTimerQueryAuxiliaryCounterFrequency)(unsigned __int64*);/* 0x1d0 4 */
long (*HalConnectThermalInterrupt)(unsigned char (*)(struct _KINTERRUPT*, void*));/* 0x1d4 4 */
unsigned char (*HalIsEFIRuntimeActive)(void);/* 0x1d8 4 */
unsigned char (*HalTimerQueryAndResetRtcErrors)(unsigned char);/* 0x1dc 4 */
void (*HalAcpiLateRestore)(void);/* 0x1e0 4 */
long (*KdWatchdogDelayExpiration)(unsigned __int64*);/* 0x1e4 4 */
long (*HalGetProcessorStats)(enum _HAL_PROCESSOR_STAT_TYPE, unsigned long, unsigned long, unsigned long*);/* 0x1e8 4 */
unsigned __int64 (*HalTimerWatchdogQueryDueTime)(unsigned char);/* 0x1ec 4 */
long (*HalConnectSyntheticInterrupt)(unsigned char (*)(struct _KINTERRUPT*, void*));/* 0x1f0 4 */
void (*HalPreprocessNmi)(unsigned long);/* 0x1f4 4 */
long (*HalEnumerateEnvironmentVariablesWithFilter)(unsigned long, unsigned char (*)(const struct _GUID*, const wchar_t*), void*, unsigned long*);/* 0x1f8 4 */
long (*HalCaptureLastBranchRecordStack)(unsigned long, struct _HAL_LBR_ENTRY*, unsigned long*);/* 0x1fc 4 */
/* ── cacheline 8 boundary (512 bytes) ── */
unsigned char (*HalClearLastBranchRecordStack)(void);/* 0x200 4 */
long (*HalConfigureLastBranchRecord)(unsigned long, unsigned long);/* 0x204 4 */
unsigned char (*HalGetLastBranchInformation)(unsigned long*, unsigned long*);/* 0x208 4 */
void (*HalResumeLastBranchRecord)(unsigned char);/* 0x20c 4 */
long (*HalStartLastBranchRecord)(unsigned long, unsigned long*);/* 0x210 4 */
long (*HalStopLastBranchRecord)(unsigned long);/* 0x214 4 */
long (*HalIommuBlockDevice)(void*);/* 0x218 4 */
long (*HalIommuUnblockDevice)(struct _EXT_IOMMU_DEVICE_ID*, void**);/* 0x21c 4 */
long (*HalGetIommuInterface)(unsigned long, struct _DMA_IOMMU_INTERFACE*);/* 0x220 4 */
long (*HalRequestGenericErrorRecovery)(void*, unsigned long*);/* 0x224 4 */
long (*HalTimerQueryHostPerformanceCounter)(unsigned __int64*);/* 0x228 4 */
long (*HalTopologyQueryProcessorRelationships)(unsigned long, unsigned long, unsigned char*, unsigned char*, unsigned char*, unsigned long*, unsigned long*);/* 0x22c 4 */
void (*HalInitPlatformDebugTriggers)(void);/* 0x230 4 */
void (*HalRunPlatformDebugTriggers)(unsigned char);/* 0x234 4 */
void* (*HalTimerGetReferencePage)(void);/* 0x238 4 */
long (*HalGetHiddenProcessorPowerInterface)(struct _HIDDEN_PROCESSOR_POWER_INTERFACE*);/* 0x23c 4 */
/* ── cacheline 9 boundary (576 bytes) ── */
unsigned long (*HalGetHiddenProcessorPackageId)(unsigned long);/* 0x240 4 */
unsigned long (*HalGetHiddenPackageProcessorCount)(unsigned long);/* 0x244 4 */
long (*HalGetHiddenProcessorApicIdByIndex)(unsigned long, unsigned long*);/* 0x248 4 */
long (*HalRegisterHiddenProcessorIdleState)(unsigned long, unsigned __int64);/* 0x24c 4 */
void (*HalIommuReportIommuFault)(unsigned __int64, struct _FAULT_INFORMATION*);/* 0x250 4 */
unsigned char (*HalIommuDmaRemappingCapable)(struct _EXT_IOMMU_DEVICE_ID*, unsigned long*);/* 0x254 4 */
};
size 600 (0x258)150 members0 holespadding 010 cachelines